1. Field of the Invention
The present invention relates to a liquid crystal display (LCD) device and more particularly to an array substrate for an LCD device and an LCD device being capable of uniformizing a signal delay in link lines, and a method of fabrication the array substrate and the LCD device.
2. Discussion of the Related Art
A related art liquid crystal display (LCD) device uses optical anisotropy and polarization properties of liquid crystal molecules. The liquid crystal molecules have a definite alignment direction as a result of their thin and long shapes. The alignment direction of the liquid crystal molecules can be controlled by applying an electric field across the liquid crystal molecules. In other words, as the intensity or direction of the electric field is changed, the alignment of the liquid crystal molecules also changes. Since incident light is refracted based on the orientation of the liquid crystal molecules due to the optical anisotropy of the liquid crystal molecules, images can be displayed by controlling light transmissivity.
Since the LCD device including a thin film transistor (TFT) as a switching element, referred to as an active matrix LCD (AM-LCD) device, has excellent characteristics of high resolution and displaying moving images, the AM-LCD device has been widely used.
The AM-LCD device includes an array substrate, a color filter substrate and a liquid crystal layer interposed therebetween. The array substrate may include a pixel electrode and the TFT, and the color filter substrate may include a common electrode. The AM-LCD device is driven by an electric field between the pixel electrode and the common electrode to have excellent properties of transmittance and aperture ratio.
FIG. 1 is a plane view of an array substrate for the related art LCD device. In FIG. 1, the array substrate includes a substrate 11, where a display region DR and a non-display region NDR at a periphery of the display region DR are defined, a gate line 13 and a data line 15. The gate line 13 crosses the data line 15 to define a pixel region in the display region DR.
Although not shown, a thin film transistor (TFT) connected to the gate and data lines 13 and 15 and a pixel electrode connected to the TFT are disposed in the pixel region P.
In the non-display region NDR, a gate drive integrated circuit (IC) 20 for applying a signal to the gate line 13 to drive the TFT and a data drive IC 30 for applying a signal to the pixel electrode through the data line 15 are disposed. In addition, a gate link line 14 for connecting the gate drive IC 20 to the gate line 13 and a data link line 16 for connecting the data drive IC 30 to the data line 15 are disposed in the non-display region NDR.
For example, the gate drive IC 20 includes first to third gate drive ICs 20a, 20b and 20c, and the gate lines 13 are connected to the first to third gate drive ICs 20a, 20b and 20c via the gate link lines 14. The data drive IC 30 includes first to fourth data drive ICs 30a, 30b, 30c and 30d, and the data lines 15 are connected to the first to fourth data drive ICs 30a, 30b, 30c and 30d via the data link lines 16.
In this case, the data link lines 16 have a difference in a length depending on a position of the data lines 16 such that a resistance deviation is generated in the data link line 16. Namely, the data link line 16 connected to the data line 15, which is adjacent to the gate drive IC 20 and connected to the first data drive IC 20a, has a different resistance than other data link lines 16. The resistance deviation is increased as a size of the substrate 11 is enlarged. This resistance deviation problem is also generated in the data link lines 16 connected to the second to fourth data drive ICs 20b, 20c and 20d. In addition, the resistance deviation problem is generated in the gate link line 14 connected to the gate drive IC 20.
A signal delay is generated by the resistance deviation problem such that a displaying image quality is degraded.
To these problems, an array substrate including a data link line or a gate link line having a zigzag shape is introduced. FIG. 2 is a plane view showing a data link line having a zigzag shape in the related art array substrate.
In FIG. 2, a data line 60 and a data drive IC 70 for applying a signal to the data line 60 are disposed on the substrate 51. In addition, a data link line 62 for connecting the data drive IC 70 to the data line 60 is disposed on the substrate 51.
The data line 60 includes first to third data lines 60a, 60b and 60c. The first to third data lines 60a, 60b and 60c are classified by a distance from the data line at a center line of the data drive IC 70, which is called as a center data line 60. Namely, the first data line 60a has a first distance from the center data line 60, the second data line 60b has a second distance, which is smaller than the first distance, from the center data line 60, and the third data line 60c has a third distance, which is smaller than the second distance, from the center data line 60. The data link line 62 is also classified into first to third data link lines 62a, 62b and 62c respectively connected to the first to third data lines 60a, 60b and 60c. Each data link lines 62a, 62b and 62c has a zigzag shape. A number of the zigzag shape is different in the first to third data link lines 62a, 62b and 62c. Namely, the first data link line 62a connected to the first data line 60a, which has the largest distance from the center data line 60, has the lowest number of zigzag shapes, while the third data link line 62c connected to the third data line 60c, which has the smallest distance from the center data line 60, has the greatest number of zigzag shapes. As a result, a length of the first to third data link lines 62a, 62b and 62c can be uniformed without regard for their distance from the center data line 60 such that a signal delay problem by a resistance deviation of the data link lines 62a, 62b and 62c can be prevented.
Unfortunately, there are still problems. Particularly, the problem appears in a narrow bezel type LCD device. In the narrow bezel type to reduce a size of the LCD device, it is required to minimize an area of the non-display region. In this case, there is a limitation for uniformizing a resistance of the data link lines by controlling a number of zigzag shapes of the data link lines.